It is often the case that the image data for a computer graphics display does not fit very efficiently into the standard sizes of memory components. For example, among the many image resolutions for computer displays in the market today, a common resolution for computer displays is 640.times.480. Such resolution for a display refers to a display having an overall screen measuring 640 pixels wide by 480 lines high. But a frame buffer of video information servicing this display at typical bit-per-pixel rates fits very inefficiently into any standard sizes of memory components, leaving large amounts of memory unused. As an illustration, referring to the frame buffer and memory size tables shown in FIGS. 1A and 1B, a 640.times.480 display at 16 bits per pixel requires 614,400 bytes to store its data, but the smallest memory size available for such a frame buffer is 1,048,576 bytes. This leaves 434,176 bytes of memory unused, enough to store a second 640.times.480 frame buffer at 8 bits per pixel.
Processor-controlled systems including an image display often have needs for more than one frame buffer in order to store additional image information from sources such as live TV video or a pen input device, allowing overlaying (or underlaying) any such external image(s) onto the normal display image. Additional frame buffers are also used in systems where there are at least two different image displays, e.g., a built-in LCD display and an external CRT monitor. For these systems operatively associating with more than one frame buffer possibly from multiple sources, the above-mentioned memory management inefficiency could be cured by appropriately storing the more than one frame buffer into a video memory system having multiple memory components, e.g., VRAMs or DRAMs.
On the one hand, VRAM is dual-ported in that image data used to refresh the display(s) are clocked out of one data port while the processor, e.g., CPU, updates the image data through another port of the VRAM. On the other hand, image data in DRAM are accessed for refresh and updates via a single port. In fact, the embodiments disclosed hereinafter are better adapted for VITAM usage but the invention can be easily re-configured by an artisan to use other types of memory including DRAM.
One implementation for managing more than one frame buffer is a video memory system using VRAM accessed by an associated CPU over a 16-bit bus, and by a video controller over a 32-bit serial data bus. This implementation treats the two 16-bit halves of the 32-bit VRAM as two separate 16-bit VRAM banks, independently accessible by the CPU over the same 16-bit data bus (separate RAS/ signals to the two VRAM banks making this possible), and independently accessible by the video controller over the two 16-bit halves of the 32-bit serial data bus (separate output clock signals to the two VRAM banks making this possible). Under this implementation, the CPU stores a first logical frame buffer into a first VRAM bank and a second logical frame buffer into a VRAM bank other than the first VRAM bank. The video controller then accesses the two logical frame buffers separately because each 16-bit half of the 32-bit serial port for VRAM data output is independently clocked. As demonstrated in FIG. 2, when logical frame buffers A and B are both stored into the memory system at the same 16 bits-per-pixel rate, using pixels from each VRAM bank at the same rate means using the data bits at the same rate, so the video controller simply clocks the 32-bit VRAM data bus port of the two VRAM banks simultaneously and the full 16 bits of each VRAM output port would be clocked once for each display pixel. Unfortunately, when using this implementation, neither frame buffer is to be larger than the maximum size that can be stored in one bank of VRAM (i.e., no larger than on half the maximum size storable in the combined banks if used as one memory). This restriction means that considerable VRAM cells remains unused, or it means that the addition of an overlay buffer reduces the maximum bits per pixel rate for the display by half.